1. Field of the Invention
The present invention relates to a method of fabricating semiconductor devices, and in particular to a method of forming an isolation region for providing space among adjacent transistors in semiconductor devices including SOI (silicon on insulator) wafers.
2. Related Art Statement
As integration in very large scale integrated circuits (VLSI) increases, an isolation region provided among adjacent transistors to electrically separate the adjacent transistors has been shrunk enormously. For instance, the size of isolation region in 4M bit DRAM is presently 0.8 micrometers. Thus, it is required to narrow the isolation region's dimension into a range of submicrons' order. Much research and development has been accomplished with respect to a method of forming isolation region for so-called "submicron devices".
One of them is a method using SOI (silicon on insulator) wafers. Various kinds of SOI wafers can be obtained. A typical SOI wafer has a single crystal silicon substrate, a silicon dioxide film laid on top of upper surface of the silicon substrate and having thickness ranging from about 0.5 to 1.0 micrometers, and a single crystal silicon layer laid on top of upper surface of the silicon dioxide film and having thickness ranging from about 0.03 to 0.5 micrometers. Such SOI wafers can be fabricated in various processes, and presently a great deal of has been accomplished.
One of typical reports of such researches is P. K. Vasudev et al., Technical Digest of VLSI Symposium 1988, page 61. FIGS. 1A and 1B are cross-sectional views of a MOS transistor fabricated on the SOI wafer as reported in the Digest, wherein FIG. 1B is a cross-sectional view taken along A--A line in FIG. 1A. Now referring to these FIGS. 1A and 1B, the MOS transistors are formed in single crystal silicon islands 103aa, 103ab disposed on upper surface of a silicon dioxide film 102 which is formed on top of a single crystal silicon substrate 101. Gate oxide films 107 cover the surfaces of the silicon islands 103aa, 103ab including their upper surfaces and side surfaces. On the gate oxide films 107 are disposed gate electrodes 109. In the silicon islands 103aa, 103ab are provided layers 108 with high impurity concentration which work as source/drain. Around the silicon islands 103aa, 103ab the silicon dioxide film 102 is exposed outside. This exposure area corresponds to an isolation region 105. A dimension of the isolation region 105 is defined as space between the silicon islands 103aa and 103ab, and depends on processing accuracy of the silicon islands 103aa, 103ab. The smaller the dimension is, the greater the increase in the level of device integration.
FIGS. 2A to 2E illustrate the steps of fabricating the MOS transistor shown in FIGS. 1A and 1B. An SOI wafer is used as a wafer. As illustrated in FIG. 2A, the SOI wafer has a single crystal silicon substrate 101, a silicon dioxide film 102 laid on top of the silicon substrate 101, and a single crystal silicon layer 103 laid on top of the silicon dioxide film 102. As illustrated in FIG. 2B, thermal oxide film 110 having a thickness of about 30 nanometers is formed over the upper surface of the single crystal silicon layer 103, and then patterned photoresist 104 is formed on top of the thermal oxide film 110. Then, the film 110 is removed by means of reactive ion etching using the photoresist 104 as a mask. Subsequently, the silicon layer 103 is entirely removed using the photoresist 104 as a mask to expose the silicon dioxide film 102, thereby a single crystal silicon island 103a and an isolation region 105 being formed as illustrated in FIG. 2C. After the removal of the photoresist 104, diluted hydrofluoric acid (HF) is used to remove the film 110 located on the upper surface of the silicon island 103a. While removing the film 110, the silicon dioxide film 102 exposed to the isolation region 105 is also etched together with the film 110. In particular, etching effect penetrates a part of silicon dioxide film 102 located beneath the periphery of the silicon island 103a. Thus, the film 102 is undercut in such a manner as illustrated in FIG. 2D. Then, as illustrated in FIG. 2E, the exposed surfaces of the silicon island 103a including its upper, side and lower surfaces are covered with the gate oxide film 107. Finally, the MOS transistor as shown in FIGS. 1A and 1B (wherein an undercut portion of the film 102 is not shown for simplicity) is fabricated using any conventional methods of fabricating MOS transistor.
According to the aforementioned method of fabricating semiconductor devices, the single crystal silicon island disposed on the silicon dioxide film has substantially right angle corners at its upper ends and lower ends. Accordingly, when the MOS transistor works, intensive concentration of electric field happens at a part of the gate oxide film applied adjacent the right angle corners of the silicon island (see FIG. 1B). Such intensive concentration of electric field causes a problem in deteriorating the reliability of the gate oxide film at the right angle corners of the silicon island. The smaller a transistor becomes and thus the thinner the gate oxide film becomes, this problem gets worse. In addition, due to the fact that the silicon island has steps and ends of these steps are so steep, the difficulty arises in step coverage of electrical wiring and insulation films among layers and so on.
Another typical method of forming an isolation region, which is used in forming semiconductor devices on an SOI wafer, is the method of using a LOCOS type field oxide film which was reported in Y. Omura et al., Digest of Technical Papers of 1985 Symposium on VLSI Technology, IEEE CAT. No. 85 CH2125-3, May 14-16, 1985/KOBE, page 24, or Electronics Letters, 9th November 1989, Vol. 25, No. 23, page 1580. In this method, a field oxide film is formed on a single crystal silicon layer of an SOI wafer by means of LOCOS process, and a single crystal silicon island is formed simultaneously with the formation of the field oxide film. Consequently, the single crystal silicon island is exposed outside only at its upper surface. Then, after a gate oxide film is formed on the upper surface of the silicon island, a MOS transistor is fabricated in conventional manners.
Though this method can solve the aforementioned problems, it brings another problems. First, this method causes a so-called bird's beak which makes the contact area narrower for connecting a diffusion layer (source/drain) to electrical wires, resulting in an increase of contact resistance. Secondarily, when the single crystal silicon island is a P-type one (an N-channel MOS transistor is fabricated in this case), the P-type impurity density near boundary area between the field oxide film and the single crystal silicon island decreases more enormously than in the LOCOS process for the conventional single crystal silicon substrate, because of the existence of the buried oxide layer which also absorbs Boron atoms during the LOCOS oxidation process. The decrease in impurity density causes a problem in increasing the leakage current between a source and a drain resulting in a decrease in the threshold voltage of the transistor.